AMD CEO Dr. In her keynote presentation on the Computex digital commerce truthful, Lisa Su introduced an innovation in chip housing know-how: 3D V-Cache. AMD has already had the Epyc processors for servers and the Ryzen processors for desktop PCs composed of a number of chip units. These sit subsequent to one another on a standard die service.
Sooner or later, nevertheless, AMD additionally desires to have two dies stacked, i.e. to open up the vertical as a 3rd dimension: The contract producer TSMC locations an extra SRAM die with an space of 36 sq. millimeters on every core complicated die (CCD). It expands the interior 32 MB L3 cache of the CCD by 64 MB to a complete of 96 MB.
Lisa Su confirmed the pattern of a prototype of a Ryzen 9 5900X with 3D V-Cache, wherein each the built-in warmth spreader (IHS) and extra silicon plates had been faraway from the left of the 2 CCDs. This makes the sq. SRAM die with an edge size of 6 mm seen.
Su emphasised that the stacked SRAM die within the completed collection product can’t be seen with the bare eye, as a result of matching silicon plates are connected to the correct and left: These serve for mechanical energy and guarantee warmth conduction from the decrease CCD to the IHS.
The completed processor should even have the identical top because the variations with out 3D V-Cache, in order that the contact strain of the cooler matches. Due to this fact, the stacked chips are thinned accordingly.
192 MB L3 cache
The beforehand hypothetical Ryzen 9 5900X with two eight-core CCDs (every with six energetic cores), every with a 32 MB L3 cache, comes with two further 64 MB SRAMs to a complete of 192 MB L3 cache. In comparison with the earlier model of the Ryzen 9 5900X with “solely” 64 MB L3 cache, the enormous cache is alleged to convey a mean of 15 p.c increased refresh charges for PC video games with full HD decision.
Lisa Su didn’t go into different CPU variations with 3D V-Cache. Prior to now few months there was hypothesis a couple of server processor with the alleged code title “Milan-X” (the Epyc 7003 known as “Milan”), which is alleged to have further HBM2 reminiscence chips. Competitor Intel is planning a number of processors with its personal in-house for 2022 Foveros stacking technology.
Stacked with out solder
The AMD boss emphasised that the Stacking technology from TSMC allows extraordinarily excessive contact densities and doesn’t use soldered connections, however quite tiny copper “bumps”. Additionally come Through-silicon vias (TSVs) to be used, i.e. vertical connections by means of a die.